Unisyn Reconfigurable Synthesizer Architecture

Features:
* Frequency Range: .1 to 2.5 GHz
* Resolution: SubHertz referenced to DDS
* Reconfigurable Subblock Interconnect provides architectural
   flexibility
* 48dB step attenuator option for amplitude control
* Onboard 89C52 microcontroller with eeprom
* Synthesizer embedded microcontroller system software
   resident in eeprom eases laboratory prototyping software demands
* Uses +15 and +5 volt from standard PC supply connector
* Serial port communications with PC
* LCD display interface with 6 button input for stand alone operation
* Fits in standard CD rom bay in PC case
* Multiple outputs for maximum resource utilization
* Uses purchased standard oscillators or onboard
   designs for economy
* Subblocks on board:
   -High Stability TCXO
   -VCXO: Phase lockable: freq: user specified
   -DDS: Clock Freq Max=125 MHz
   -Simple phase lock loop
    Freq: user specified .1 to 2.5 GHz band resolution=sub hertz
   -Offset phase lock loop
    Freq: user specified .1 to 2.5 GHz band: resolution=sub hertz
   -48 dB step attenuator
   -On board microcontroller with eeprom with block write

Reconfigurable Synthesizer Circuit Board-Shown without shields installed
Click for bigger picture

Description

Click here to view block diagram of Unisyn synthesizer architecture
Approximate cost versus option and quantity

The reconfigurable architecture of the Unisyn synthesizer implements a flexible economical solution for RF production environment signal generation. This solution replaces many applications in the testing environment where laboratory grade signal generators are used but at a fraction of the cost. This eliminates the lost productivity of switch over time from signal generator resource sharing and in turn generates better return on investment due to more production capacity being up and ready simultaneously.

This architecture contains the capability to provide local oscillator generation for dual conversion up and down converters. With one of the local oscillators being referenced to the DDS the IF scheme has below 1 hertz frequency step resolution. This makes it an ideal candidate for laboratory full scale mock up of RF conversion schemes.

End user may specifies frequency band of interest step size at time of purchase for factory configurations. Applications are limited to on the order of 1 octave in bandwidth. Lab breadboard applications can leave this open and self configure.

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Contact Information:
Phone: 602 414 0641 (USA)
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